Implementation of SKLANSKY Tree Adder using Quasi Static Adiabatic Logic

This paper presents the design for low power circuilts which use reversible logic to conserve energy. The project presents the implementation of a Sklansky tree adder structure using a quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The SKLANSKY Tree adder structure has been chosen due to its increased fan-out that results in reduced latency and improved speed performance. The performance characteristics of the CEPAL tree adder are compared against the conventional static CMOS of 130 nm technology logic is to identify its adiabatic power advantage. In this we design the 4-bit CEPAL and CMOS using Sklansky tree adder and thus results in the 30% of power saving over static CMOS. Keywords– CMOS, CEPAL, Adiabatic Tree Logic, Static Adiabatic logic, SKLANSKY Tree adder, ERL.